1. Field of the Invention
This invention relates to application specific integrated circuit (ASIC) design and particularly to the ASICs having large capacity of DRAM in a multi-node computer system, that needs to restrain overall power consumptions.
2. Description of Background
Power consumption has been one of the major battle areas for today's digital chip and system design. Demand for faster chips and bigger DRAM capacity is pushing the power supply to its capacity limit. How to keep the average DRAM current consumption low while maintain high system performance and efficiency brings to a significant challenge to today's system design. Heretofore, IBM provided the power governor control logic for a RAM subsystem of a computer processor, by utilizing the control logic described in IBM U.S. Pat. No. 6,667,929 of Vesselina K. Zaharinova-Papazova et al, incorporated herein by reference, which provides power governor control logic for a DRAM (Dynamic Random Access Memory) subsystems for indirectly measuring actual power consumption and decreasing the power consumption when the consumption exceeds a preset amount. This patent describes a way to count the number of memory accesses within a DRAM refresh period. If the total count exceeds a predefined threshold, then the power governor will be activated and thus slows down the subsequence memory access by artificially inserting idle commands between memory fetches and stores. Refer to FIG. 1 of this application for the block diagram of the implementation. The IBM z990 mainframe is the first system that equipped with this power governor. The z990 system has maximum capacity of four total nodes and each node can have up to four independent memory arrays. There are a maximum of eight power governors in a system to control those memory arrays independently.
Since those power governors work independently, they do not have the complete awareness of the power usage for the entire system. We have learned that in an extreme case, a single memory access could burst into just one memory array in a node, while other memory arrays in the system are idle. The power governor belonging to this particular memory array could be activated, and its subsequent memory accesses slow down. However, the average memory activities and total current consumption in the whole system might still be well under the limit. In this case, the memory performance deteriorates unnecessarily. The memory system is not running at its maximum throughput.